Power MOSFETs are widely used in numerous applications, including automotive electronics, disk drives and power supplies. Generally, these devices function as switches, and they are used to connect a power supply to a load. It is important that the resistance of the device be as low as possible when the switch is closed. Otherwise, power is wasted and excessive heat may be generated.
A common type of power MOSFET currently in use is a planar, double-diffused (DMOS) device, illustrated in the cross-sectional view of FIG. 1. An electron current flows laterally from N+ source regions 12 through channel regions formed within P-body regions 14 into an N-epitaxial layer 16. Current flow in the channel regions is controlled by a gate 18. After the current leaves the channel regions, it flows downward through N-epitaxial layer 16 into an N+ substrate 20, which forms the drain of the device. A parasitic junction field effect transistor (JFET) is formed by the existence of P-body regions 14 on either side of an intervening region of N-epitaxial layer 16. A depletion zone 22 adjacent the junction between each of P-body regions 14 and N-epitaxial layer 16 tends to squeeze the current and thereby increase the resistance in this area. As the current proceeds downward through N-epitaxial layer 16 it spreads out and the resistance decreases.
In an alternative form of vertical current flow device, the gate is formed in a "trench". Such a device is illustrated in FIG. 2A, which is a cross-sectional view of a single cell of a MOSFET 100, and in FIG. 2B, which is a plan view of the cell. Gates 102 and 104 are formed in trenches and surrounded by gate oxide layers 106 and 108, respectively. The trenched gate is often formed in a grid pattern (one section of which is shown in FIG. 2B), the grid representing a single interconnected gate, but a trench gate may also be formed as a series of distinct parallel stripes.
MOSFET 100 is a double-diffused device which is formed in an N-epitaxial layer 110. An N+ source region 112 is formed at the surface of epitaxial layer 110, as is a P+ contact region 114. A P-body 116 is located below N+ source region 112 and P+ contact region 114. A metal source contact 118 makes contact with the N+ source region 112 and shorts the N+ source region 112 to the P+ contact region 114 and P body 116.
The N-epitaxial layer 110 is formed on an N+ substrate 120, and a drain contact (not shown) is located at the bottom of the N+ substrate 120. The contact for the gates 102 and 104 is likewise not shown, but it is generally made by extending the conductive gate material outside of the trench and forming a metal contact at a location remote from the individual cells. The gate is typically made of polysilicon doped with phosphorus or boron.
A region 111 of N-epitaxial layer 110 between the N+ substrate 120 and the P body 116 is generally more lightly doped with N-type impurities than is N+ substrate 120. This increases the ability of MOSFET 100 to withstand high voltages. Region 111 is sometimes referred to as a "lightly doped" or "drift" region ("drift" referring to the movement of carriers in an electric field). Drift region 111 and N+ substrate 120 constitute the drain of MOSFET 100.
MOSFET 100 is an N-channel MOSFET. When a positive voltage is applied to gate 102, a channel region within P-body 116 adjacent the gate oxide 106 becomes inverted and, provided there is a voltage difference between the N+ source region 112 and the N+ substrate 120, an electron current will flow from the source region through the channel region into the drift region 111. In drift region 111, some of the electron current spreads diagonally at an angle until it hits the N+ substrate 120, and then it flows vertically to the drain. Other portions of the current flow straight down through the drift region 111, and some of the current flows underneath the gate 102 and then downward through the drift region 111.
The gate 102 is doped with a conductive material. Since MOSFET 100 is an N-channel MOSFET, gate 102 could be polysilicon doped with phosphorus. Gate 102 is insulated from the remainder of MOSFET 100 by the gate oxide 106. The thickness of gate oxide 106 is chosen to set the threshold voltage of MOSFET 100 and may also influence the breakdown voltage of MOSFET 100. The breakdown voltage of a power MOSFET such as MOSFET 100 would typically be no greater than 200 volts and more likely 60 volts or less.
One feature that makes the trench configuration attractive is that, as described above, the current flows vertically through the channel of the MOSFET. This permits a higher packing density than MOSFETs in which the current flows horizontally through the channel. Greater cell density generally means more MOSFETs per unit area of the substrate and, since the MOSFETs are connected in parallel, the on-resistance of the device is reduced.
In MOSFET 100 shown in FIG. 2A, the P+ contact region 114 is quite shallow and does not extend to the lower junction of the P-body region 116. This helps ensure that P-type dopant does not get into the channel region, where it would tend to increase the threshold voltage of the device and cause the turn-on characteristics of the device to vary from one run to another depending on the alignment of the P+ contact region 114. However, with a shallow P+ region 114, the device can withstand only relatively low voltages (e.g., 10 volts) when it is turned off. This is because the depletion spreading around the junction between P-body region 116 and drift region 111 does not adequately protect the corners of the trench (e.g., corner 122 shown in FIG. 1A). As a result, avalanche breakdown may occur in the vicinity of the trench, leading to a high generation rate of carriers which can charge or degrade the gate oxide 106 or even, in an extreme case, cause a rupture in the gate oxide 106. Thus the MOSFET 100 shown in FIG. 1B is at best a low voltage device.
FIG. 2C illustrates a modification of MOSFET 100 in which the P+ body contact region 114 is extended downward slightly beyond the lower junction of P-body region 116. The higher concentration of P ions in this region increases the size of the depletion area, and this provides some additional shielding around the corner 122 of the trench. However, if this device is pushed into breakdown, the generation of carriers will still most likely occur near gate oxide layer 106, and this could lead to the impairment of the gate oxide as described above.
The breakdown situation was significantly improved in the arrangement shown in FIGS. 3A-3C, which was described in U.S. Pat. No. 5,072,266 to Bulucea et al. In MOSFET 300, the P+ region 114 is extended downward below the bottom of the trench to form a deep, heavily-doped P region at the center of the cell. While this provides additional shielding at corner 122, the primary advantage is that carrier generation occurs primarily at the bottom tip 302 of the P+ region 114. This occurs because the electric field is strengthened beneath the tip 302, thereby causing carriers to be generated at that point or along the curvature of the junction rather than adjacent the gate oxide 106. This reduces the stress on gate oxide 106 and improves the reliability of MOSFET 300 under high voltage conditions, even though it may reduce the actual junction breakdown of the device.
FIG. 3B illustrates a perspective cross-sectional view of the left half of the cell shown in FIG. 3A, as well as portions of the adjoining cells. FIG. 3C shows a comparable P-channel device. FIG. 3D illustrates how a gate metal 121 may be used to form a connection with gates 102 and 104.
The deep central P+ region 114 in MOSFET 300, while greatly reducing the adverse consequences of breakdown, also has some unfavorable effects. First, an upward limit on cell density is created, because with increasing cell density P ions may be introduced into the channel region. As described above, this tends to increase the threshold voltage of the MOSFET. Second, the presence of a deep P+ region 114 tends to pinch the electron current as it leaves the channel and enters the drift region 111. In an embodiment which does not include a deep P+ region (as shown in, for example, FIG. 2A), the electron current spreads out when it reaches the drift region 111. This current spreading reduces the average current per unit area in the drift region 111 and therefore reduces the on-resistance of the MOSFET. The presence of a deep central P+ region limits this current spreading and increases the on-resistance consistent with high cell densities.
What is needed, therefore, is a MOSFET which combines the breakdown advantages of a deep central P+ region with a low on-resistance.